Publications
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- pubyear
- 2018
- creators
- Pinxten, J. van; Geilen, M.; Hendriks, M.; Basten, T.
Parametric Critical Path Analysis for Event Networks with Minimal and Maximal Time Lags
- published_in
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(10)
High-end manufacturing systems are cyber-physical systems where productivity depends on the close cooperation of mechanical (physical) and scheduling (cyber) aspects. Mechanical and control constraints impose minimal and maximal time differences between events in the product flow. Sequence-dependent constraints are used by a scheduler to optimize system productivity while satisfying operational requirements.
- pubyear
- 2018
- creators
- Behrouzian, A.R.B.; Goswami, D.; Basten, T.; Geilen, M.; Alizadeh Ara, H.; Hendriks, M.
Firmness Analysis of Real-Time Applications Under Static-Priority Preemptive Scheduling
(m, k)-firm real-time tasks must meet the deadline of at least m jobs out of any k consecutive jobs to satisfy the firmness requirement. Scheduling of an (m, k)-firm task requires firmness analysis, whose results are used to provide system-level guarantees on the satisfaction of firmness conditions. We address firmness analysis of an (m, k)-firm task that is intended to be added to a set of asynchronous tasks scheduled under a Static-Priority Preemptive (SPP) policy.
- pubyear
- 2018
- creators
- Ara, H.A.; Behrouzian, A.; Hendriks, M.; Geilen, M.; Goswami, D.; Basten, T.
Scalable analysis for multi-scale dataflow models
- published_in
- ACM Transactions on Embedded Computing Systems, 17(4)
Multi-scale dataflow models have actors acting at multiple granularity levels, e.g., a dataflow model of a video processing application with operations on frame, line, and pixel level. The state of the art timing analysis methods for both static and dynamic dataflow types aggregate the behaviours across all granularity levels into one, often large iteration, which is repeated without exploiting the structure within such an iteration.
- pubyear
- 2018
- creators
- Sioutas, S.; Stuijk, S.; Corporaal, H.; Basten, A.A.; Somers, L.
Loop transformations leveraging hardware prefetching
Memory-bound applications heavily depend on the bandwidth of the system in order to achieve high performance. Improving temporal and/or spatial locality through loop transformations is a common way of mitigating this dependency. However, choosing the right combination of optimizations is not a trivial task, due to the fact that most of them alter the memory access pattern of the application and as a result interfere with the efficiency of the hardware prefetching mechanisms present in modern architectures.
- pubyear
- 2018
- creators
- Dams, D.R.; Grumberg, O.
Abstraction and abstraction refinement
Abstraction, in the context of model checking, is aimed at reducing the state space of the system by omitting details that are irrelevant to the property being verified. Many successful approaches to the "state explosion problem," some of them described in other chapters, can be seen as abstractions. In this chapter, several notions of abstraction are considered in a uniform setting.
- pubyear
- 2018
- creators
- Dams, D.; Mooij, A.J.; Kramer, P.; Radulescu, A.; Vanhara, J.
Model-based software restructuring: lessons from cleaning up COM interfaces in industrial legacy code
- published_in
- 25th IEEE International Conference on Software Analysis, Evolution and Reengineering, SANER 2018, 20-23 March 2018, Campobasso, Italy, pp. 552-556.
The high-tech industry is faced with ever growing amounts of software to be maintained and extended. To keep the associated costs under control, there is a demand for more human overview and for large-scale code restructurings. Language technology such as parsing can assist in this, but classical restructuring tools are typically not flexible enough to accommodate the needs of specific cases.
- pubyear
- 2018
- creators
- Awan, M.A.; Souto, P.; Bletsas, K.; Akesson, B.; Tovar, E.
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation
Mixed-criticality multicore system design must often guarantee both safety and high performance. Memory bandwidth regulation among different cores can be a useful tool for guaranteeing safety, as it mitigates the interference when accessing main memory. The use of mode changes and system models like Vestal’s can help provide both safety, for critical functions, and scheduling performance, by efficiently utilising the platform.
- pubyear
- 2018
- creators
- Awan, M.A.; Souto, P.; Bletsas, K.; Akesson, B.; Tovar, E.
Mixed-criticality Scheduling with Memory Bandwidth Regulation
Mixed-criticality (MC) multicore system design must reconcile safety guarantees and high performance. The interference among cores on shared resources in such systems leads to unpredictable temporal behaviour. Memory bandwidth regulation among different cores can be a useful tool to mitigate the interference when accessing main memory.
- pubyear
- 2018
- creators
- Schuts, M.; Hooman, J.; Tielemans, P.
Industrial Experience with the Migration of Legacy Models using a DSL
Software departments of companies that exist for several decades often have to deal with legacy models. Important business assets have been modelled with tools that are no longer preferred within the company. Manually remodelling these models with a new tool would be too costly. In this paper, we describe an approach to migrate from Rhapsody models to models of another tool.
- pubyear
- 2018
- creators
- Akesson, B.; Hooman, J.; Dekker, R.; Ekkelkamp, W.; Stottelaar, B.
Pain-mitigation Techniques for Model-based Engineering using Domain-specific Languages
Changing an established way of working can be a real headache. This is particularly true if there are high stakes involved, e.g., when changing the development process for complex systems. New design methods, such as model-based engineering (MBE) using domain-specific languages (DSLs) promise significant gains, such as cost reductions and improvements in productivity and product quality.